Currently, emerging integrated circuit (IC) assemblies may include three dimensional (3D) package architecture where one or more dies (e.g., memory dies) are stacked on another die (e.g., a system-on-chip die). The stacked dies may overhang the underlying die in some configurations, which may result in risks of defects such as cracking of the stacked dies. Currently, shrink scaling of the underlying die or the overhang may be undesirably restricted in order to mitigate such risks. Additionally, as IC assemblies continue to shrink to smaller dimensions, it may be desirable to provide a smaller Z-height of a 3D package architecture for smaller devices such as mobile devices.